1. Field of the Disclosure
The present disclosure relates generally to a digital signal processor, and more particularly, to a digital signal processor using a signed magnitude method and a mobile receiver having the same.
2. Description of the Related Art
An attempt has been made to embody a portion or all of a baseband modem in a digital signal processor (DSP) on account of a size of an integrated circuit or chip used in a mobile communication field and flexibility in specification change or a reduction in a development period of a chip.
Methods of expressing fixed point binary data in a DSP include a two's (2's) complement method, a one's (1's) complement method, or a signed magnitude method. The 2's complement method is adopted in order to embody an efficient adder in other fields in addition to a mobile communication field.
However, since most input and output data used in a mobile communication algorithm characteristically form a Gaussian distribution centered about zero, the input/output data frequently transit from a positive number to a negative number or from a negative number to a positive number. As a result, power loss in a baseband modem is generated due to toggling of a sign bit(s) of the input/output data.